Mitigating a voltage condition of a memory cell in a memory sub-system

ABSTRACT

A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.

RELATED APPLICATIONS

This application is a divisional under 35 U.S.C. § 120 of U.S. patentapplication Ser. No. 16/045,641, filed on Jul. 25, 2018, which claimsthe benefit under 35 U.S.C. § 119(e) of U.S. Provisional PatentApplication No. 62/628,198, filed on Feb. 8, 2018, which areincorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally relates to a memory sub-system, andmore specifically, relates to mitigating a voltage condition of a memorycell in a memory sub-system.

BACKGROUND

A memory sub-system can be a storage system, such as a solid-state drive(SSD), and can include one or more memory components that store data.The memory components can be, for example, non-volatile memorycomponents and volatile memory components. In general, a host system canutilize a memory sub-system to store data at the memory components andto retrieve data from the memory components.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousimplementations of the disclosure.

FIG. 1 illustrates an example computing environment that includes amemory sub-system in accordance with some embodiments of the presentdisclosure.

FIG. 2 is a flow diagram of an example method to perform an operation ona memory cell to change a voltage condition of the memory cell inaccordance with some embodiments of the present disclosure

FIG. 3 illustrates voltage conditions or states of a memory cell inaccordance with some embodiments of the present disclosure.

FIG. 4 is a flow diagram of an example method to determine whether toperform an operation on a memory cell to change a voltage conditionbased on other memory cells in accordance with some embodiments of thepresent disclosure.

FIG. 5A illustrates operations on proximate memory cells that change thevoltage condition of a particular memory cell in accordance with someembodiments of the present disclosure.

FIG. 5B illustrates operations on proximate memory cells that thatchange the voltage condition of the particular memory cell so that thevoltage condition is to be mitigated in accordance with some embodimentsof the present disclosure.

FIG. 6 is a flow diagram of an example method to determine whether toperform the operation on the memory cell to change a voltage conditionbased on an elapsed time in accordance with some embodiments of thepresent disclosure.

FIG. 7 is a flow diagram of an example method to mitigate a voltagecondition of a memory cell based on a read offset in accordance withsome embodiments of the present disclosure.

FIG. 8 is a block diagram of an example computer system in whichimplementations of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to mitigating a voltagecondition of a memory cell in a memory sub-system. A memory sub-systemis also hereinafter referred to as a “memory device.” An example of amemory sub-system is a storage system, such as a solid-state drive(SSD). In some embodiments, the memory sub-system is a hybridmemory/storage sub-system. In general, a host system can utilize amemory sub-system that includes one or more memory components. The hostsystem can provide data to be stored at the memory sub-system and canrequest data to be retrieved from the memory sub-system.

Each memory component can include multiple memory cells where eachmemory cell can store one or more bits of binary data corresponding todata received from the host system. A conventional memory sub-system canstore the data at a particular memory cell by performing two programmingpasses (or any number of programming passes) that each program or storedata at the memory cell. For example, a first programming pass canprogram data at the memory cell at a particular time. At a later time, asecond programming pass can be performed on the memory cell to storeadditional data at the memory cell and the second programming passrequires and uses the information stored in the first pass programming.A certain amount of time can elapse between the memory sub-systemperforming the first programming pass and performing the secondprogramming pass on the same memory cell.

The state or condition of the memory cell can change during the amountof time that has elapsed between the memory sub-system performing thefirst programming pass and the second programming pass on the memorycell. For example, the memory cell can be at an initial voltagecondition after the first programming pass is used to perform aprogramming operation on the memory cell. The initial voltage conditioncorresponds to a transient threshold voltage (V_(t)) state. In someembodiments, the transient V_(t) state can be a physical state of thememory cell where electrons of the memory cell are distributedthroughout the memory cell. After the first programming pass has beenperformed and time elapses and other operations are not performed on thememory cell, the memory cell can transition from the initial voltagecondition or state to another voltage condition or state. For example,the memory cell can transition to a stable threshold voltage (V_(t))state which corresponds to another physical state of the memory cellwhere the electrons of the memory cell are not distributed throughoutthe memory cell. Instead, the electrons can be distributed towards theedges or exterior of the memory cell.

The changing of the voltage condition of the memory cell from thetransient V_(t) state to the stable V_(t) state can result in the datastored at the memory cell by the first programming pass beingincorrectly read or retrieved when performing the second programmingpass. For example, the data that was programmed to the memory cell bythe first programming pass will subsequently be read from the memorycell and used to store the additional data at the memory cell during thesecond programming pass. However, if the memory cell has transitionedfrom the transient V_(t) state to the stable V_(t) state after the firstprogramming pass was performed on the memory cell and before the secondprogramming pass is performed on the memory cell, then errors can bemore frequent in the data read from the memory cell. As such, thetransient V_(t) state can correspond to a state of the memory cell wheredata stored at the memory cell can be read or retrieved with a decreasederror rate when compared with the stable V_(t) state where the datastored at the memory cell can be read or retrieved with an increasederror rate. Thus, in a conventional memory sub-system, an increased useof error detection and correction operations (i.e., error controloperations) should be performed to correct the errors in the data beforeprogramming additional data to the memory cell as part of the secondprogramming pass. The increased use of the error control operation canresult in a reduction of performance of the conventional memorysub-system as fewer read operations and write operations from the hostsystem can be performed while additional error control operations arebeing performed by the memory sub-system.

Furthermore, in other conventional memory systems, if no error controloperation is performed on the data that was stored from the first passprogramming before the second pass programming is performed, then thedata can include a larger number of bit errors if a corresponding memorycell is in the stable Vt state, resulting in write-in errors for thedata. Such write-in errors can deteriorate the correction capability ofan error correction operation that uses soft (i.e., reliability)information associated with the data.

Aspects of the present disclosure address the above and otherdeficiencies by mitigating a voltage condition of a memory cell at amemory sub-system. For example, an operation (e.g., a read operation)can be performed on the memory cell between the performance of the firstprogramming pass on the memory cell and the performance of the secondprogramming pass on the memory cell to start the transition of thememory cell from the stable V_(t) state to the transient V_(t) state.Thus, the second programming pass can then be performed when the memorycell is at the transient V_(t) state and is associated with a decreasederror rate.

In some embodiments, the performance of the operation to transition thestate of a particular memory cell can be based on other programmingpasses or operations that have been performed on other memory cells thatare proximate to the particular memory cell. For example, the firstprogramming pass can be performed to store data at the particular memorycell and subsequently other programming passes or operations (e.g.,write operations or erase operations) can be performed on other memorycells that are proximate in location to the particular memory cell. Suchoperations performed on the other memory cells can influence the memorycell to transition from the transient V_(t) state to the stable V_(t)state. For example, write operations performed on adjacent or proximatememory cells (e.g., other memory cells on the same plane or die of theparticular memory cell) can contribute to the particular memory celltransitioning from the transient V_(t) state to the stable V_(t) state.As more operations are performed on the proximate memory cells, then theparticular memory cell may transition to the stable V_(t) state morequickly. In some embodiments, a read operation can be performed on theparticular memory cell after a threshold number of programming and eraseoperations have been performed on the proximate memory cells. The readoperation can thus initiate the transition of the particular memory cellfrom the stable V_(t) state to the transient V_(t) state. In the same oralternative embodiments, the read operation can be performed on theparticular memory cell if a threshold amount of time has elapsed sincethe first programming pass has been performed on the particular memorycell and before any second programming pass has been performed on theparticular memory cell.

Advantages of the present disclosure include, but are not limited to, anincreased performance of the memory sub-system as fewer error controloperations are to be performed when writing data to the memorysub-system. For example, the second programming pass can be performed onthe memory cell when the memory cell is at the transient V_(t) statewhen the data stored at the memory cell from the first programming passcan be read with fewer errors. Additionally, the reliability of datastored at the memory cell can be improved as the second programming passis then performed on the memory cell when the memory cell is at thetransient V_(t) state.

FIG. 1 illustrates an example computing environment 100 that includes amemory sub-system 110 in accordance with some embodiments of the presentdisclosure. The memory sub-system 110 can include media, such as memorycomponents 112A to 112N. The memory components 112A to 112N can bevolatile memory components, non-volatile memory components, or acombination of such. In some embodiments, the memory sub-system is astorage system. An example of a storage system is a SSD. In someembodiments, the memory sub-system 110 is a hybrid memory/storagesub-system. In general, the computing environment 100 can include a hostsystem 120 that uses the memory sub-system 110. For example, the hostsystem 120 can write data to the memory sub-system 110 and read datafrom the memory sub-system 110.

The host system 120 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, or suchcomputing device that includes a memory and a processing device. Thehost system 120 can include or be coupled to the memory sub-system 110so that the host system 120 can read data from or write data to thememory sub-system 110. The host system 120 can be coupled to the memorysub-system 110 via a physical host interface. As used herein, “coupledto” generally refers to a connection between components, which can be anindirect communicative connection or direct communicative connection(e.g., without intervening components), whether wired or wireless,including connections such as electrical, optical, magnetic, etc.Examples of a physical host interface include, but are not limited to, aserial advanced technology attachment (SATA) interface, a peripheralcomponent interconnect express (PCIe) interface, universal serial bus(USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. Thephysical host interface can be used to transmit data between the hostsystem 120 and the memory sub-system 110. The host system 120 canfurther utilize an NVM Express (NVMe) interface to access the memorycomponents 112A to 112N when the memory sub-system 110 is coupled withthe host system 120 by the PCIe interface. The physical host interfacecan provide an interface for passing control, address, data, and othersignals between the memory sub-system 110 and the host system 120.

The memory components 112A to 112N can include any combination of thedifferent types of non-volatile memory components and/or volatile memorycomponents. An example of non-volatile memory components includes anegative-and (NAND) type flash memory. Each of the memory components112A to 112N can include one or more arrays of memory cells such assingle level cells (SLCs) or multi-level cells (MLCs) (e.g., triplelevel cells (TLCs) or quad-level cells (QLCs)). In some embodiments, aparticular memory component can include both an SLC portion and a MLCportion of memory cells. Each of the memory cells can store one or morebits of data (e.g., data blocks) used by the host system 120. Althoughnon-volatile memory components such as NAND type flash memory aredescribed, the memory components 112A to 112N can be based on any othertype of memory such as a volatile memory. In some embodiments, thememory components 112A to 112N can be, but are not limited to, randomaccess memory (RAM), read-only memory (ROM), dynamic random accessmemory (DRAM), synchronous dynamic random access memory (SDRAM), phasechange memory (PCM), magneto random access memory (MRAM), negative-or(NOR) flash memory, electrically erasable programmable read-only memory(EEPROM), and a cross-point array of non-volatile memory cells. Across-point array of non-volatile memory can perform bit storage basedon a change of bulk resistance, in conjunction with a stackablecross-gridded data access array. Additionally, in contrast to manyflash-based memories, cross-point non-volatile memory can perform awrite in-place operation, where a non-volatile memory cell can beprogrammed without the non-volatile memory cell being previously erased.Furthermore, the memory cells of the memory components 112A to 112N canbe grouped as memory pages or data blocks that can refer to a unit ofthe memory component used to store data.

The memory system controller 115 (hereinafter referred to as“controller”) can communicate with the memory components 112A to 112N toperform operations such as reading data, writing data, or erasing dataat the memory components 112A to 112N and other such operations. Thecontroller 115 can include hardware such as one or more integratedcircuits and/or discrete components, a buffer memory, or a combinationthereof. The controller 115 can be a microcontroller, special purposelogic circuitry (e.g., a field programmable gate array (FPGA), anapplication specific integrated circuit (ASIC), etc.), or other suitableprocessor. The controller 115 can include a processor (processingdevice) 117 configured to execute instructions stored in local memory119. In the illustrated example, the local memory 119 of the controller115 includes an embedded memory configured to store instructions forperforming various processes, operations, logic flows, and routines thatcontrol operation of the memory sub-system 110, including handlingcommunications between the memory sub-system 110 and the host system120. In some embodiments, the local memory 119 can include memoryregisters storing memory pointers, fetched data, etc. The local memory119 can also include read-only memory (ROM) for storing micro-code.While the example memory sub-system 110 in FIG. 1 has been illustratedas including the controller 115, in another embodiment of the presentdisclosure, a memory sub-system 110 may not include a controller 115,and may instead rely upon external control (e.g., provided by anexternal host, or by a processor or controller separate from the memorysub-system).

In general, the controller 115 can receive commands or operations fromthe host system 120 and can convert the commands or operations intoinstructions or appropriate commands to achieve the desired access tothe memory components 112A to 112N. The controller 115 can beresponsible for other operations such as wear leveling operations,garbage collection operations, error detection and error-correcting code(ECC) operations, encryption operations, caching operations, and addresstranslations between a logical block address and a physical blockaddress that are associated with the memory components 112A to 112N. Thecontroller 115 can further include host interface circuitry tocommunicate with the host system 120 via the physical host interface.The host interface circuitry can convert the commands received from thehost system into command instructions to access the memory components112A to 112N as well as convert responses associated with the memorycomponents 112A to 112N into information for the host system 120.

The memory sub-system 110 can also include additional circuitry orcomponents that are not illustrated. In some embodiments, the memorysub-system 110 can include a cache or buffer (e.g., DRAM) and addresscircuitry (e.g., a row decoder and a column decoder) that can receive anaddress from the controller 115 and decode the address to access thememory components 112A to 112N.

The memory sub-system 110 can include a voltage condition component 113(e.g., circuitry, dedicated logic, programmable logic, firmware, etc.)to perform an operation on a memory cell to change a voltage conditionof the memory cell. In some embodiments, the controller 115 includes atleast a portion of the voltage condition component 113. For example, thecontroller 115 can include a processor 117 (processing device)configured to execute instructions stored in local memory 119 forperforming the operations described herein. In some embodiments, thevoltage condition component 113 is part of the host system 110, anapplication, or an operating system.

In some implementations, the voltage condition component 113 can performan operation on memory cells at the memory components 112A to 112N totransition memory cells from a state of an increased error rate (e.g.,the stable V_(t) state) to another state of a decreased error rate(e.g., the transient V_(t) state). Further details with regards to theoperations of the voltage condition component 113 are described below.

FIG. 2 is a flow diagram of an example method to perform an operation ona memory cell to change a voltage condition of the memory cell inaccordance with some embodiments of the present disclosure. The method200 can be performed by processing logic that can include hardware(e.g., a processing device, circuitry, dedicated logic, programmablelogic, microcode, hardware of a device, etc.), software (e.g.,instructions run or executed on a processing device), or a combinationthereof. In some embodiments, the method 200 is performed by the voltagecondition component 113 of FIG. 1. Although shown in a particularsequence or order, unless otherwise specified, the order of theprocesses can be modified. Thus, the illustrated embodiments should beunderstood only as examples, and the illustrated processes can beperformed in a different order, and some processes can be performed inparallel. Additionally, one or more processes can be omitted in variousembodiments. Thus, not all processes are required in every embodiment.Other process flows are possible.

As shown in FIG. 2, at block 210, the processing logic identifies that aprogramming operation has been performed on a memory cell. In someembodiments, the programming operation is performed on a data block thatincludes a group of memory cells. As such, operations described hereincan be performed on a data block (e.g., a group of memory cells) and/orindividual memory cells. For example, the operations described withrespect to a memory cell in the present disclosure can also be used witha data block that is a group of memory cells. The programming operationcan be performed as part of a first programming pass that programs dataat the memory cell of a memory component in a memory sub-system. Thefirst programming pass can be part of a two-pass programming operationthat includes a second programming pass that programs additional data atthe memory cell after the first programming pass has been performed onthe memory cell. At block 220, the processing logic identifies that asubsequent programming operation has not been performed on the memorycell. For example, the memory sub-system can identify that the secondprogramming pass has not been performed on the memory cell (e.g., timehas elapsed since the first programming pass). At block 230, theprocessing logic determines that a voltage condition of the memory cellhas changed. For example, the voltage condition can correspond towhether the memory cell has changed from the transient V_(t) state tothe stable V_(t) state. For example, the memory sub-system can identifywhether a threshold number of program/erase operations have beenperformed at other memory cells that are proximate to the memory cell.Further details with regards to determining whether the voltagecondition of the memory cell has changed (e.g., from the transient V_(t)state to the stable V_(t) state) based on the threshold number ofoperations being performed at proximate memory cells are described withregards to FIGS. 4, 5A, and 5B. In the same or alternative embodiments,the memory sub-system can identify that the voltage condition of thememory cell has changed based on a threshold amount of time elapsingsince the first programming pass was performed on the memory cell.Further details with regards to determining whether the voltagecondition of the memory cell has changed based on the threshold amountof time elapsing are described with regards to FIG. 6. In someembodiments, the memory sub-system can infer or assume that the voltagecondition of the memory cell has changed based on the threshold numberof operations being performed at proximate memory cells and/or thethreshold amount of time elapsing since the first programming pass wasperformed on the memory cell.

At block 240, the processing logic performs an operation on the memorycell when the voltage condition of the memory cell has changed torestore the voltage condition of the memory cell. For example, theperformance of the operation on the memory cell can restore the memorycell to be at the transient V_(t) state when the memory cell has changedto the stable V_(t) state. The operation can be, but is not limited to,a read operation that is performed on the memory cell. In someembodiments, the operation can be the application of a voltage to thememory cell or any other operation or action that results in a voltagebeing applied to the memory cell. At block 250, the processing logicperforms the subsequent programming operation on the memory cell afterthe operation is performed to restore the voltage condition of thememory cell. The subsequent programming operation can be the secondprogramming pass to store additional data at the memory cell when thememory cell has transitioned back to the transient V_(t) state. Thesecond programming pass uses the data stored at the memory cell that wasprogrammed during the first memory pass.

FIG. 3 illustrates voltage conditions or states of a memory cell inaccordance with some embodiments of the present disclosure. In general,various operations of FIG. 3 can be performed on the memory cell by thevoltage condition component 113 of FIG. 1.

As shown in FIG. 3, a first programming operation 310 can be performedon a memory cell. For example, the first programming operation 310 canstore data at the memory cell as part of a first programming pass. Insome embodiments, the memory cell can store data corresponding tomultiple memory pages and the first programming pass can store datacorresponding to a portion of the memory pages. The memory cell 320 canbe at an initial state after the first programming operation 310 isperformed on the memory cell 320. For example, the memory cell 320 canbe at the transient V_(t) state when the data is programmed to thememory cell 320. As time elapses or other program/erase operations areperformed on proximate memory cells, the memory cell 320 can progresstowards the stable V_(t) state. Thus, the memory cell can transitionfrom a state where data stored at the memory cell can be read with fewererrors (e.g., a decreased error rate corresponding to the transientV_(t) state) to a state where data stored at the memory cell can be readwith more errors (e.g., an increased error rate corresponding to thestable V_(t) state). After the memory cell 320 has transitioned to thestable V_(t) state, a read operation 330 (or another type of operationthat applies a voltage to the memory cell 320) can be performed on thememory cell 320 to mitigate the stable V_(t) state of the memory cell.For example, the read operation 330 can restore the transient V_(t)state of the memory cell 320. The memory cell 320 can be restored to thetransient V_(t) state after an amount of time that is dependent on thetemperature of the memory system. In some embodiments, the second passprogramming can be initiated or can start after the amount of time haselapsed so that the memory cell is in the transient V_(t) state. Thesecond programming operation 340 can be performed on the memory cell 320after the read operation 330 has been performed on the memory cell 320to restore the transient V_(t) state or to initiate a restoration of thetransient V_(t) state. Thus, the second programming operation 340 can beperformed on the memory cell 320 after the memory cell 320 has beenrestored to the transient V_(t) state.

FIG. 4 is a flow diagram of an example method 400 to determine whetherto perform an operation on a memory cell to change a voltage conditionof the memory cell based on other memory cells in accordance with someembodiments of the present disclosure. In general, the method 400 can beperformed by processing logic that can include hardware (e.g., aprocessing device, circuitry, dedicated logic, programmable logic,microcode, hardware of a device, etc.), software (e.g., instructions runor executed on a processing device), or a combination thereof. Themethod 400 can be performed by voltage condition component 113 of FIG.1.

As shown in FIG. 4, at block 410, the processing logic determines that aprogramming operation is to be performed on a particular memory cell.The programming operation can be part of a second programming pass. Forexample, the particular memory cell can store data from a priorprogramming operation from a first programming pass that was performedat a prior time prior time and does not yet store data from a secondprogramming pass. At block 420, the processing logic identifies a numberof operations that have been performed on memory cells that areproximate to the particular memory cell. The memory cells that are on asame word line, same plane, and/or a same die as the particular memorycell may be considered to be proximate to the particular memory cell. Insome embodiments, memory cells that are within a particular distance ofthe particular memory cell may be considered to be proximate memorycells. The operations that have been performed on the proximate memorycells can include programming operations (e.g., the storing of data) atthe proximate memory cells and/or erase operations to remove data at theproximate memory cells. At block 430, the processing logic determineswhether the number of operations satisfies a threshold number. Thenumber of operations performed on the proximate memory cells can beconsidered to satisfy the threshold number (i.e., a threshold condition)when the number of operations is equal to or exceeds the thresholdnumber and the number of operations can be considered to not satisfy thethreshold number when the number of operations is less than thethreshold number. If the number of operations satisfies the thresholdnumber or the threshold condition, then at block 440, the processinglogic performs a read operation on the particular memory cell. Forexample, the read operation can be performed on the particular memorycell to change the voltage condition of the particular memory cell froma state of increased errors for the data read at the memory cell (e.g.,the stable V_(t) state) to another state of decreased errors for thedata read at the memory cell (e.g., the transient V_(t) state). At block450, the processing logic performs the programming operation on theparticular memory cell. For example, data can be programmed to theparticular memory cell after the read operation has been performed onthe particular memory cell to change the voltage condition of theparticular memory cell.

Referring to FIG. 4, if the number of operations performed on theproximate memory cells satisfies the threshold number or the thresholdcondition, then at block 460, then the processing logic determines tonot perform a read operation on the particular memory cell. For example,a determination can be made to not perform the read operation totransition the particular memory cell to the transient V_(t) state asthe memory cell can be assumed to not be at the stable V_(t) state. Insome embodiments, other read operations from a host system to retrievedata stored at the particular memory cell can be performed while a readoperation intended to transition the particular memory cell to thetransient V_(t) state is not to be performed. At block 470, theprocessing logic performs the programming operation on the particularmemory cell. For example, additional data can be stored at theparticular memory cell as part of the second programming pass.

FIG. 5A illustrates operations on memory cells of proximate data blocksthat change the voltage condition of memory cells in a particular datablock in accordance with some embodiments of the present disclosure. Ingeneral, the voltage condition component 113 of FIG. 1 can change thevoltage condition of the memory cells of the particular data block basedon operations that have been performed on proximate data blocks.

As shown in FIG. 5A, data can be stored at a particular data block 550.In some embodiments, a data block includes a group of memory cells. Datablocks 510, 520, 530, 540, 560, 570, 580, and 590 are proximate to theparticular data block cell 550 (e.g., on the same word line, plane, ordie). A number of operations performed at the proximate data blocks canbe used to determine whether to perform the read operation on theparticular memory data block 550 to restore the voltage condition of theparticular data block 550. For example, one operation has been performedon the memory cells of the data block 510, two operations have beenperformed on the memory cells of the data block 560, and threeoperations have been performed on the memory cells of the data block580. Thus, the number of operations performed on data blocks that areproximate to the particular data block 550 is six operations. Each ofthe six operations can contribute towards the memory cells of theparticular data block 550 progressing to the stable V_(t) state. Theparticular data block 550 can be assumed to be at the stable V_(t) statewhen a threshold number of operations have been performed at theproximate data blocks. For example, if the threshold number is ten, thenthe six operations that have been performed on the proximate data blocksdo not exceed the threshold number of operations. As such, theparticular data block can be considered to still be at the transientV_(t) state.

FIG. 5B illustrates operations on proximate data blocks that change thevoltage condition of the particular data blocks so that the voltagecondition is to be mitigated in accordance with some embodiments of thepresent disclosure. In general, the voltage condition component 113 ofFIG. 1 can change the voltage condition of the particular data blockbased on operations that have been performed on proximate data blocks.

As shown in FIG. 5B, ten operations have been performed on the memorycells of the proximate data blocks. Since the ten operations is equal tothe threshold number, then the operations that have been performed onthe proximate data blocks can be considered to have changed the voltagecondition of the memory cells of the particular data block 550 to thestable V_(t) state. As such, a read operation can be performed on theparticular data block 550 to transition the memory cells of theparticular data block 550 from the stable V_(t) state to the transientV_(t) state. In some embodiments, the read operation can be performed oneach memory cell of the particular data block 550.

FIG. 6 is a flow diagram of an example method 600 to determine whetherto perform the operation on the memory cell to change a voltagecondition based on an elapsed time in accordance with some embodimentsof the present disclosure. In general, the method 600 can be performedby processing logic that can include hardware (e.g., a processingdevice, circuitry, dedicated logic, programmable logic, microcode,hardware of a device, etc.), software (e.g., instructions run orexecuted on a processing device), or a combination thereof. The method600 can be performed by voltage condition component 113 of FIG. 1.

As shown in FIG. 6, at block 610, the processing logic identifies that afirst programming operation has been performed on a memory cell. Thefirst programming operation can be part of a first programming pass thatstores data at the memory cell of a data block. Furthermore, theprocessing logic can determine that another programming operation of asecond programming pass to store additional data at the memory cell hasnot yet been performed at the memory cell. At block 620, the processinglogic determines an amount of time that has elapsed since the firstprogramming operation was performed on the memory cell. The amount oftime that has elapsed can correspond to an assumption that the memorycell has transitioned from the transient V_(t) state to the stable V_(t)state. In the same or alternative embodiments, the amount of time thathas elapsed can correspond to when a read operation should be performedto keep memory cells of the data block at the transient V_(t) state. Atblock 630, the processing logic determines whether the amount of timeexceeds a threshold amount of time. The memory cells of the data blockcan be assumed to have transitioned from the transient V_(t) state tothe stable V_(t) state when the amount of time that has elapsed exceeds(or is equal to) the threshold amount of time (i.e., a threshold timecondition). In some embodiments, the threshold amount of time cancorrespond to an amount of time that a memory sub-system with a memorycomponent that includes the data block has been powered off or notoperating. If the amount of time that has elapsed since the firstprogramming operation was performed on the memory cell of the data blockexceeds the threshold amount of time, then at block 640, the processinglogic performs a read operation on the memory cell to change the voltagecondition of the memory cell. The read operation can be an operationthat is performed without a request from a host system to retrieve datastored at the memory cell. At block 650, the processing logic performs asecond programming operation on the memory cell. For example, the secondprogramming operation can be performed after the read operation isperformed on the memory cell to change the voltage condition of thememory cell or to keep the voltage condition of the memory cell.Otherwise, if the amount of time that has elapsed since the firstprogramming operation was performed on the memory cell does not exceedthe threshold amount of time, then at block 660, the processing logicdetermines to not perform the read operation on the memory cell of thedata block. Furthermore, at block 670, the processing logic performs thesecond programming operation on the memory cell.

In some embodiments, the read operation can be performed on each memorycell of a data block that was not programmed with a second programmingpass at memory components of the memory sub-system. The read operationscan be performed on the memory cells when the memory sub-system hasinitialized or powered back on after being powered off or not inoperation for the threshold amount of time.

FIG. 7 is a flow diagram of an example method 700 to mitigate a voltagecondition of a memory cell based on a read offset in accordance withsome embodiments of the present disclosure. In general, the method 700can be performed by processing logic that can include hardware (e.g., aprocessing device, circuitry, dedicated logic, programmable logic,microcode, hardware of a device, etc.), software (e.g., instructions runor executed on a processing device), or a combination thereof. Themethod 700 can be performed by voltage condition component 113 of FIG.1.

Aspects of the present disclosure may mitigate the voltage condition ofthe memory cell by applying a read offset that is used to perform a readoperation on a particular memory cell that has been assumed to havechanged from the transient V_(t) state to the stable V_(t) state. Forexample, as described below, instead of changing the voltage conditionof a memory cell that may have transitioned to the stable V_(t) state, aread offset value can be used to retrieve data stored at the memory cellwhen the memory cell is considered to have transitioned from thetransient V_(t) state to the stable V_(t) state.

As shown in FIG. 7, at block 710, the processing logic identifies that aprogramming operation has been performed to store data at a memory cell.For example, the first programming pass can be performed on the memorycell. At block 720, the processing logic determines that the memory cellhas changed voltage conditions. The memory cell can be determined tohave changed from the transient V_(t) state to the stable V_(t) statewhen a threshold condition is satisfied. For example, the thresholdcondition can be satisfied when a threshold number of operations havebeen performed on proximate memory cells or when a threshold amount oftime has elapsed since the programming operation was performed to storethe data at the memory cell, as previously described. At block 730, theprocessing logic receives a read offset based on the changed voltagecondition. The read offset can specify a particular threshold voltage toapply to read the data stored at the memory cell that was programmedduring the first programming pass. For example, a first thresholdvoltage can be applied to read data stored at the memory cell when thememory cell is at a transient V_(t) state and a different secondthreshold voltage based on the read offset can be applied to read thedata stored at the memory cell when the memory cell is at the stableV_(t) state.

At block 740, the processing logic performs a read operation to retrievedata at the memory cell based on the read offset. For example, the datacan be retrieved from the memory cell by applying a threshold voltage tothe memory cell that is defined by the read offset. Thus, the secondprogramming pass can be performed by reading the data from the memorycell at the stable V_(t) state by applying a threshold voltage that isdifferent than the threshold voltage to be applied when reading the datafrom the memory cell at the transient V_(t) state. At block 750, theprocessing logic performs a subsequent programming operation on thememory cell based on the data retrieved from the read operation. Forexample, a second programming pass can be performed on the memory cellwhere the additional data stored at the memory cell from the secondprogramming pass is based on values of the data of the first programmingpass performed on the memory cell at an earlier time.

FIG. 8 illustrates an example machine of a computer system 800 withinwhich a set of instructions, for causing the machine to perform any oneor more of the methodologies discussed herein, can be executed. In someembodiments, the computer system 800 can correspond to a host system(e.g., the host system 120 of FIG. 1) that includes, is coupled to, orutilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1)or can be used to perform the operations of a controller (e.g., toexecute an operating system to perform operations corresponding to thevoltage condition component 113 of FIG. 1). In alternative embodiments,the machine can be connected (e.g., networked) to other machines in aLAN, an intranet, an extranet, and/or the Internet. The machine canoperate in the capacity of a server or a client machine in client-servernetwork environment, as a peer machine in a peer-to-peer (ordistributed) network environment, or as a server or a client machine ina cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 800 includes a processing device 802, a mainmemory 804 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM(RDRAM), etc.), a static memory 806 (e.g., flash memory, static randomaccess memory (SRAM), etc.), and a data storage system 818, whichcommunicate with each other via a bus 830.

Processing device 802 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 802 can also be one or more special-purpose processing devicessuch as an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. The processing device 802 is configuredto execute instructions 826 for performing the operations and stepsdiscussed herein. The computer system 800 can further include a networkinterface device 808 to communicate over the network 820.

The data storage system 818 can include a machine-readable storagemedium 824 (also known as a computer-readable medium) on which is storedone or more sets of instructions 826 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 826 can also reside, completely or at least partially,within the main memory 804 and/or within the processing device 802during execution thereof by the computer system 800, the main memory 804and the processing device 802 also constituting machine-readable storagemedia. The machine-readable storage medium 824, data storage system 818,and/or main memory 804 can correspond to the memory sub-system 110 ofFIG. 1.

In one embodiment, the instructions 826 include instructions toimplement functionality corresponding to a voltage condition component(e.g., the voltage condition component 113 of FIG. 1). While themachine-readable storage medium 824 is shown in an example embodiment tobe a single medium, the term “machine-readable storage medium” should betaken to include a single medium or multiple media that store the one ormore sets of instructions. The term “machine-readable storage medium”shall also be taken to include any medium that is capable of storing orencoding a set of instructions for execution by the machine and thatcause the machine to perform any one or more of the methodologies of thepresent disclosure. The term “machine-readable storage medium” shallaccordingly be taken to include, but not be limited to, solid-statememories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, read-only memories (ROMs), random access memories (RAMs), EPROMs,EEPROMs, magnetic or optical cards, or any type of media suitable forstoring electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems can be used with programs in accordance with the teachingsherein, or it can prove convenient to construct a more specializedapparatus to perform the method. The structure for a variety of thesesystems will appear as set forth in the description below. In addition,the present disclosure is not described with reference to any particularprogramming language. It will be appreciated that a variety ofprogramming languages can be used to implement the teachings of thedisclosure as described herein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer). In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aread only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader spirit and scope of embodiments of thedisclosure as set forth in the following claims. The specification anddrawings are, accordingly, to be regarded in an illustrative senserather than a restrictive sense.

What is claimed is:
 1. A method comprising: determining that a first programming operation has been performed on a memory cell; identifying an amount of time that has elapsed since the first programming operation has been performed on the memory cell; determining whether the amount of time that has elapsed satisfies a threshold time condition; and in response to determining that the amount of time that has elapsed satisfies the threshold time condition, performing, by a processing device, an operation on the memory cell to change or maintain a voltage condition of the memory cell.
 2. The method of claim 1, wherein the operation on the memory cell to change or maintain the voltage condition of the memory cell corresponds to changing the memory cell from a state associated with an increased error rate to another state associated with a decreased error rate or maintaining the memory cell at the another state associated with the decreased error rate.
 3. The method of claim 2, wherein the state associated with the increased error rate is a stable threshold voltage state of the memory cell, and wherein the another state associated with the decreased error rate is a transient threshold voltage state of the memory cell.
 4. The method of claim 1, further comprising: determining that a second programming operation has not been performed on the memory cell, wherein the performing of the operation on the memory cell to change or maintain the voltage condition of the memory cell is further in response to determining that the second programming operation has not been performed on the memory cell.
 5. The method of claim 1, wherein the amount of time that has elapsed satisfies the threshold time condition when the amount of time is equal to or exceeds a threshold amount of time.
 6. The method of claim 1, further comprising: in response to determining that the amount of time that has elapsed does not satisfy the threshold time condition, determining to not perform the operation on the memory cell to change or maintain the voltage condition of the memory cell.
 7. The method of claim 1, wherein the first programming operation stores data at the memory cell, and wherein the identified amount of time that has elapsed corresponds to an elapsed time since the data was stored at the memory cell without a subsequent programming and read operation being performed at the memory cell.
 8. A system comprising: a memory; and a processing device communicably coupled to the memory, the processing device to perform operations comprising: determining that a first programming operation has been performed on a memory cell; identifying an amount of time that has elapsed since the first programming operation has been performed on the memory cell; determining whether the amount of time that has elapsed satisfies a threshold time condition; and in response to determining that the amount of time that has elapsed satisfies the threshold time condition, performing an operation on the memory cell to change or maintain a voltage condition of the memory cell.
 9. The system of claim 8, wherein the operation on the memory cell to change or maintain the voltage condition of the memory cell corresponds to changing the memory cell from a state associated with an increased error rate to another state associated with a decreased error rate or maintaining the memory cell at the another state associated with the decreased error rate.
 10. The system of claim 9, wherein the state associated with the increased error rate is a stable threshold voltage state of the memory cell, and wherein the another state associated with the decreased error rate is a transient threshold voltage state of the memory cell.
 11. The system of claim 10, wherein the operations further comprise: determining that a second programming operation has not been performed on the memory cell, wherein the performing of the operation on the memory cell to change or maintain the voltage condition of the memory cell is further in response to determining that the second programming operation has not been performed on the memory cell.
 12. The system of claim 8, wherein the amount of time that has elapsed satisfies the threshold time condition when the amount of time is equal to or exceeds a threshold amount of time.
 13. The system of claim 8, wherein the operations further comprise: in response to determining that the amount of time that has elapsed does not satisfy the threshold time condition, determining to not perform the operation on the memory cell to change or maintain the voltage condition of the memory cell.
 14. The system of claim 8, wherein the first programming operation stores data at the memory cell, and wherein the identified amount of time that has elapsed corresponds to an elapsed time since the data was stored at the memory cell without a subsequent programming and read operation being performed at the memory cell.
 15. A non-transitory machine-readable storage medium storing instructions that cause a processing device to perform operations comprising: determining that a first programming operation has been performed on a memory cell; identifying an amount of time that has elapsed since the first programming operation has been performed on the memory cell; determining whether the amount of time that has elapsed satisfies a threshold time condition; and in response to determining that the amount of time that has elapsed satisfies the threshold time condition, performing an operation on the memory cell to change or maintain a voltage condition of the memory cell.
 16. The non-transitory machine-readable storage medium of claim 15, wherein the operation on the memory cell to change or maintain the voltage condition of the memory cell corresponds to changing the memory cell from a state associated with an increased error rate to another state associated with a decreased error rate or maintaining the memory cell at the another state associated with the decreased error rate.
 17. The non-transitory machine-readable storage medium of claim 16, wherein the state associated with the increased error rate is a stable threshold voltage state of the memory cell, and wherein the another state associated with the decreased error rate is a transient threshold voltage state of the memory cell.
 18. The non-transitory machine-readable storage medium of claim 17, wherein the operations further comprise: determining that a second programming operation has not been performed on the memory cell, wherein the performing of the operation on the memory cell to change or maintain the voltage condition of the memory cell is further in response to determining that the second programming operation has not been performed on the memory cell.
 19. The non-transitory machine-readable storage medium of claim 17, wherein the amount of time that has elapsed satisfies the threshold time condition when the amount of time is equal to or exceeds a threshold amount of time.
 20. The non-transitory machine-readable storage medium of claim 17, wherein the operations further comprise: in response to determining that the amount of time that has elapsed does not satisfy the threshold time condition, determining to not perform the operation on the memory cell to change or maintain the voltage condition of the memory cell. 